Clock recovery circuits for telecommunications applications, and industrial and automotive control applications require digital and analog phase locked loop circuits to generate clock and timing signals from a reference frequency. For example, clock signals may be generated in this manner for microprocessors that control certain automobile functions, such as instrument panel displays, window controls, anti-lock brakes, engine functions, etc. Phase locked loop circuits used in these applications use a phase detector that is typically exclusive-OR (XOR) gate-based, which possess the desirable characteristic of good noise immunity. Because noise in the typical operating environment may corrupt the reference frequency, the phase locked loop may lock to the wrong frequency at twice or half of the reference frequency, for example, or lose lock entirely. Further, because there is no mechanism to detect the loss of lock or to regain lock onto the correct reference frequency, the resultant clock signal may cause the controlled apparatus or function to malfunction and fail.
One solution to this problem is to detect a loss of lock condition and then requiring the phase locked loop to go through a complete reset cycle. However, this solution causes the system to go off line. Further, it is difficult to implement a loss of lock detector in a high noise environment that does not generate erroneous results.